TSAI FEI GWO (Total 55 Patents Found)

Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to gen...
A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet...
Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the secon...
A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteri...
A developing method includes rotating a wafer. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved from a first position to a second position. The first position and the second position are over the wafer and within a perimeter of the wafer when viewed from a top o...
A method for forming a patterned target layer from a blanket target layer while employing a blanket photoresist layer in conjunction with an exposure method which is susceptible to a proximity effect employs when exposing the blanket photoresist layer to form an exposed blanket photoresist layer a main latent pattern a...
A lithography cluster includes at least two lithography cells having a first lithography cell and a second lithography cell, an interface unit configured to integrate with the first lithography cell and the second lithography cell. The first lithography cell includes a first track and a first exposing tool and a second...
A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteri...
A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves b...
A lithography cluster includes at least two lithography cells having a first lithography cell and a second lithography cell, an interface unit configured to integrate with the first lithography cell and the second lithography cell. The first lithography cell includes a first track and a first exposing tool and a second...
A lithographic apparatus for forming a patterned resist layer and a method for forming a microelectronic product both employ a lithographic exposure tool controller designed to: (1) receive input data for at least one non-environmental variable that influences an exposure dose when forming a patterned resist layer from...
The present disclosure provides a method that includes capturing a first image of a mask in a first exposure apparatus using a first exposure source and a first imaging sensor; capturing a second image of the mask in a second exposure apparatus using a second exposure source and a second imaging sensor; comparing the f...
A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form ...
A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for d...
A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on...
The present invention provides an apparatus, a method for manufacturing the apparatus, and a method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelect...
An apparatus, method for manufacturing the apparatus, and method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelectric film portion and a tip disposed...
Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the secon...
A lithographic apparatus for forming a patterned resist layer and a method for forming a microelectronic product both employ a lithographic exposure tool controller designed to: (1) receive input data for at least one non-environmental variable that influences an exposure dose when forming a patterned resist layer from...
The present disclosure provides a method that includes capturing a first image of a mask in a first exposure apparatus using a first exposure source and a first imaging sensor; capturing a second image of the mask in a second exposure apparatus using a second exposure source and a second imaging sensor; comparing the f...
A multi-step cleaning procedure cleans phase shift photomasks and other photomasks and Mo-containing surfaces. In one embodiment, vacuum ultraviolet (VUV) light produced by an Xe 2 excimer laser converts oxygen to ozone that is used in a first cleaning operation. The VUV/ozone clean may be followed by a wet SC1 chemic...
A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves b...
A new method is provided for E-beam exposure. A new method is provided for variable shaped E-beam (VSB) and Gaussian laser and E-beam exposure systems. The conventional main pattern is, under the method of the invention involving VSB, surrounded on all sides by a dummy frame whereby the dummy frame limits the beam size...
PURPOSE: A method for determining an overlay error and a control system for dynamically controlling the position of a reticle are provided to increase the density of a feature by reducing the size of a technical node. CONSTITUTION: A feature and an area boundary of the entire layout are determined (502). An initial mea...
一种确定覆盖误差的方法。该方法包括将图案从中间掩模转印至晶圆以及选择第一组数据点以测量中间掩模上的部件与晶圆上的部件之间的位置差。该方法还包括确定第一组数据点但包含较少数据点的第二组数据点。控制系统使用第二组数据...
A novel composite layer structure method which is suitable for reducing post-exposure delay (PED) effects associated with fabricating a photolithography reticle or mask and eliminating or at least minimizing variations between intended and realized critical dimension values for a circuit pattern fabricated on the retic...
A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet...
A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for d...
Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to gen...
A photomask having dies relating to different functionalities is disclosed. A photomask for performing lithography in conjunction with fabrication of one or more semiconductor devices includes one or more first semiconductor dies and one or more second semiconductor dies. Each first semiconductor die relates to first f...
A photomask having dies relating to different functionalities is disclosed. A photomask for performing lithography in conjunction with fabrication of one or more semiconductor devices includes one or more first semiconductor dies and one or more second semiconductor dies. Each first semiconductor die relates to first f...
Protecting the transparent substrate of a photomask when repairing opaque defects of the mask is disclosed. The photomask includes an opaque defect on a transparent substrate. The photomask is coated with photoresist. The mask is backside-exposed to a light source, to expose the photoresist where it is unblocked by the...
A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form ...
웨이퍼 기판을 노출시키기 위한 방법은, 디바이스 패턴을 갖는 레티클을 형성하는 단계를 포함한다. 노광 툴의 마스크 필드와 디바이스 패턴 간의 상대 배향(relative orientation)은 마스크 필드 이용에 기반하여 결정된다. 레티클은 노광 툴 상에...
A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for d...
The invention discloses a hybrid multi-layer photo-mask set which can expose layer structure of a semiconductor substrate to manufacture an integrated circuit element and a manufacturing method thereof. The layer structure is at least divided into a first subset and a second subset. The hybrid photo-mask set comprises ...
The invention calculates an optimum etch recipe for etching a product pattern in an opaque material of a photolithographic exposure mask with the objective of achieving optimum CD performance of the product pattern. If, for this optimum etch recipe, the optimum CD performance cannot be achieved, dummy patterns are adde...
本发明是有关于一种混合式多层光罩组及其制造方法,其可对半导体基材的层结构进行曝光,以制造集成电路元件。这些层结构至少区分为第一子集和第二子集。混合式光罩组包含多层光罩以及投产光罩。多层光罩包含多个图案以及间隙,这...
A novel composite layer structure method which is suitable for reducing post-exposure delay (PED) effects associated with fabricating a photolithography reticle or mask and eliminating or at least minimizing variations between intended and realized critical dimension values for a circuit pattern fabricated on the retic...
An apparatus, method for manufacturing the apparatus, and method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelectric film portion and a tip disposed...
Systems and methods are provided for edge bead removal. A laser beam of approximately a wavelength is received. The laser beam is delivered along a predetermined beam path. The laser beam is projected on an edge portion of a wafer for edge bead removal....
A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orienta...
A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for d...
The invention calculates an optimum etch recipe for etching a product pattern in an opaque material of a photolithographic exposure mask with the objective of achieving optimum CD performance of the product pattern. If, for this optimum etch recipe, the optimum CD performance cannot be achieved, dummy patterns are adde...
A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second...
This invention provides a method of using an electron beam exposure system having an electron beam with a variable shape to form patterns in a layer of resist on a substrate, a mask substrate or an integrated circuit wafer, while maintaining adequate critical dimension control and beam stability. This is accomplished b...